Hi! This is my resume
pdf version available here
Education
- Ph.D. Student in Electrical and Computer Engineering, Duke University, 2023 - Now
- M.S. in Computer Science and Information Engineering, National Cheng Kung University, 2022
- B.E. in Computer Engineering, University of Hong Kong, 2018
Research experiences
Publications
Teaching
Honors & Awards
- 2022: IEEE Taipei Section Best Dissertation Award
- 2022: IEEE Tainan Section Best Master Thesis Award
- 2022: Master Thesis Award from Institute of Information and Computing Machinery (IICM)
- 2014 - 2018: HKU Foundation Scholarship for International Students
- 2016 - 2017: Reaching Out Award scholarship from HKSAR gov.
- 2018: IEEE Hong Kong Final Year Project Merit Award
Projects
- SPEAR: A 1.25 GHz bandwidth real-time RF testbed
- SPEAR is an SDR platform based on the Xilinx RFSoC ZCU216 evaluation board capable of supporting real-time streaming of signals with a bandwidth of up to 1.25 GHz employing the direct RF radio architecture.
- It comes with an DSP pipeline written in Python and reaches the 3GPP EVM requirement of 3.5% with 256QAM modulation.
- Github: https://github.com/functions-lab/SPEAR
- A SW/HW co-designed RISC-V CNN accelerator for mask detection
- RISC-V core consists of: pipelined RV32I core, I-cache/D-cache, AXI bus, DMA, DRAM/ROM controller, Interrupt manager. It also handles the booting sequence, data movements, the control of acceleration unit, and system interrupts.
- Apply network compression and quantization on a mask detection CNN model.
- Inference the compressed CNN model on an HW acceleration unit.
- Github: https://github.com/WeiCheng14159/VSD_CNN_accelerator
- Contribute to ria-jit (an open source RISC-V to x86 binary translator)
- Find and fix a divide by zero bug with RISC-V compliance tests.
- Contribute to srv32 (an open source 3-stage pipeline RV32IM core)
- Verify and contribute RV32C instructions to the existing implementation.
Other Experiences
- Cell-based Digital IC tapeout, Taiwan Semiconductor Research Institute
- Design, tapeout, and verification of an UMC 0.18 um process chip
- Class representative for Computer Engineering major students during 2015-2016, 2017-2018
Skills
- Programming: Python, C++/C, Verilog/SystemVerilog
- AI Frameworks: Pytorch, TensorFlow
- EDA tools: NCSim, Design Compiler, IC Compiler/Innovus, Virtuoso
- Miscellaneous: Linux, Shell, Latex, Markdown, Git
Languages
- Native Mandarian, Taiwanese
- Fluent English, Cantonese